1. Field of the Invention
The invention is related to integrated circuit comparators and, more particularly, to integrated circuit comparators which operate with relatively low supply voltages.
2. Description of the Related Art
Comparators are used in a wide variety of applications such as squaring circuits, zero crossing detectors, oscillators, and voltage level detectors. Comparators are sometimes described as one-bit analog to digital converters and are important components within analog-to-digital converters of all resolutions. They are also employed within control circuits, to switch on lights and heaters, to control the operation of pumps, and to enable a switching power supply's oscillator. These are just a few of the myriad areas in which comparators find application.
Comparators are, in a first order analysis, simply differential amplifiers with positive feedback. Positive feedback takes the amplifier out of the linear region of operation, and promotes rapid switching from one output state to another. Positive feedback also adds hysteresis to the amplifier, thereby ensuring that the output won't swing wildly from one state to another due to minor noise disturbances at the differential in-puts. For a more detailed description of comparators, see Paul Horowitz, Winfield Hill, The Art of Electronics, Cambridge University Press, New York, 1989, Pages 229-231.
FIG.1 illustrates the basic components of a comparator 9. A differential input stage 10 provides inverting and non-inverting inputs (marked - and +, respectively). The differential input stage is composed, primarily, of a balanced differential amplifier 12 that is connected to amplify a differential input signal Vdiff imposed across the comparator's inverting and noninverting inputs. The amplifier 12 provides a gain G1 for amplification of the input signal Vdiff. Since the amplifier 12 is balanced, in a first order analysis, no offset compensation is required, i.e., a differential input signal Vdiff will produce a differential output signal at the output of the differential input stage, Vout=(Vdiff)(G1). However, some comparators include an offset circuit 13, discussed in greater detail in relation to FIG.2, that produces a predetermined comparator output in some circumstances. Unfortunately, the offset circuit 13 creates an input offset that adds an error component to the differential input voltage Vdiff. The output of the differential input stage is connected to an output stage 14 which includes a differential to single-ended converter 16 and a positive feedback circuit 18 which provides the comparator 9 with hysteresis. Although, for convenience, the differential to single-ended converter 16 and positive feedback circuit 18 are drawn separately, they may, in fact, be implemented as a single circuit.
One could also view the positive feedback circuit 18 as a flip-flop, or cross-coupled inverters. To analyze the effect of the comparator's positive feedback, first assume that the output of the comparator is at its "positive rail", Vsat+. A portion of the output voltage is fed back, within the output stage 14 in this example, to effectively produces a variable offset which opposes changes in the comparator's output state. That is, to change the output from Vsat+ to Vsat-, not only must the inverting terminal voltage be greater than that at the noninverting terminal, it must be greater by at least the fedback signal. Similarly, once the output signal has swung to the comparator's negative rail, the voltage at the noninverting terminal must exceed that at the inverting terminal by an amount at least equal to the fedback signal in order to change the comparator's output voltage back to the positive output rail, Vsat+.
In the following illustrative examples, which employ pnp transistors, the transistor control terminals are bases and are labeled bx, one of each transistor's current conduction terminals, the collector, is labeled cx and each transistor's other current conduction terminal, the emitter, is labeled ex. As is known in the art, differential amplifiers may, in alternative implementations employ npn transistors, or n-channel or p-channel FETs, with appropriate substitution of control and conduction terminals.
FIG.2 is a schematic diagram which illustrates the differential input stage 10 in greater detail. The balanced differential amplifier 12 includes a differential pair of transistors Q1, Q2 the bases of which b1 and b2 act as the inverting and noninverting inputs, respectively, of the comparator 9. Emitters e1 and e2 of the transistors Q1 and Q2, respectively, are connected through a bias current source I1 to a positive supply bus V+. Collectors c1 and c2 of the transistors Q1 and Q2 are connected, respectively, through load resistors R1 and R2 to a negative supply bus V- (naturally, either supply bus, V+ or V-, may, under the appropriate circumstances, be referenced to "ground"). The differential output is taken from the collectors c1 and c2. The transistors Q1 and Q2 are matched, that is, they are equal-sized transistors and yield substantially the same collector current for a given base-emitter voltage. Additionally, the resistors R1 and R2 are equal valued resistors.
The gain of the differential amplifier 12 is approximately equal to RC/re, where RC is the collector resistance, given by the value of R1 or R2 and re is the transistors' intrinsic emitter resistance, given by:
re =kT/qIc PA1 k=Boltzmann's constant PA1 T=temperature Kelvin PA1 q=the electron charge PA1 Ic=the transistor's collector current
where:
Assuming, for example, a temperature of 293 K., a collector current of 10 .mu.A, and 20 k .OMEGA. load resistors, the gain of the differential amplifier would be approximately 8. The gain may be adjusted by adjusting the collector current Ic.
As described in the discussion related to FIG.1, the differential output of the differential input stage 10 is coupled to an output stage with hysteresis and, in order to change the output state of a comparator which employs the differential input stage 10, a differential input signal must be of sufficient magnitude to overcome the comparator's built in hysteresis. Although in normal operation this may not seem too daunting a task, in some situations the comparator may fail to operate in this manner. In particular, if the input signal is at one extreme of the comparator's common mode input range, the differential pair 12 may go into dropout, shutting off. That is, if the input signals at the inverting and noninverting inputs are too high to provide sufficient base-emitter voltages for transistors Q1 and Q2, the transistors Q1 and Q2 will turn off. Without the offset circuitry composed of a current source I2, and resistors R3 and R4, whenever the differential amplifier enters dropout the comparator output, because of positive feed-back, would remain in whatever state it was in immediately prior to dropout. The offset circuitry, a current source I2 connected from the positive supply terminal V+ through a resistor divider composed of resistors R3 and R4 to the negative supply terminal V-, produces an offset voltage that forces the comparator output to a predetermined state whenever the differential amplifier 12 enters dropout.
The differential amplifier may enter dropout either because the input signals exceed a specified level or because the comparator's supply voltage drops to a level which does not provide sufficient "headroom" for the input amplifier 12 to operate. Under certain circumstances this could lead to disastrous results. In a control application, for example, whenever the comparator input stage is in dropout, the controlled process may be operating "open loop", or effectively without control. Whether the parameter being controlled is the pressure within a hydrogen tank, the temperature of a greenhouse, or the voltage output of a voltage regulator, allowing the process to run open loop could have costly, and possibly fatal, consequences. Systems which operate from low voltage supplies are particularly susceptible, e.g., as battery voltages fall, to this form of failure.
However, the offset which forces the comparator output to a predetermined state also creates, as mentioned in the discussion related to FIG.1, an offset error signal at the input to the comparator, thus requiring additional compensation circuitry.